if ( _vmx_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS )
{
min = 0;
- opt = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
+ opt = (SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
+ SECONDARY_EXEC_WBINVD_EXITING);
_vmx_secondary_exec_control = adjust_vmx_controls(
min, opt, MSR_IA32_VMX_PROCBASED_CTLS2);
}
}
case EXIT_REASON_INVD:
+ case EXIT_REASON_WBINVD:
{
- inst_len = __get_instruction_length(); /* Safe: INVD */
+ inst_len = __get_instruction_length(); /* Safe: INVD, WBINVD */
__update_guest_eip(inst_len);
if ( !list_empty(&(domain_hvm_iommu(v->domain)->pdev_list)) )
+ {
wbinvd();
+ /* Disable further WBINVD intercepts. */
+ if ( (exit_reason == EXIT_REASON_WBINVD) &&
+ (vmx_cpu_based_exec_control &
+ CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) )
+ __vmwrite(SECONDARY_VM_EXEC_CONTROL,
+ vmx_secondary_exec_control &
+ ~SECONDARY_EXEC_WBINVD_EXITING);
+ }
break;
}
extern u32 vmx_vmentry_control;
#define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
+#define SECONDARY_EXEC_WBINVD_EXITING 0x00000040
extern u32 vmx_secondary_exec_control;
extern bool_t cpu_has_vmx_ins_outs_instr_info;
#define EXIT_REASON_IO_INSTRUCTION 30
#define EXIT_REASON_MSR_READ 31
#define EXIT_REASON_MSR_WRITE 32
-
#define EXIT_REASON_INVALID_GUEST_STATE 33
#define EXIT_REASON_MSR_LOADING 34
-
#define EXIT_REASON_MWAIT_INSTRUCTION 36
#define EXIT_REASON_MONITOR_INSTRUCTION 39
#define EXIT_REASON_PAUSE_INSTRUCTION 40
-
#define EXIT_REASON_MACHINE_CHECK 41
-
#define EXIT_REASON_TPR_BELOW_THRESHOLD 43
#define EXIT_REASON_APIC_ACCESS 44
+#define EXIT_REASON_WBINVD 54
/*
* Interruption-information format